1. Field of the Invention
This invention relates to fabrication methods for integrated circuit electrode structures and particularly to techniques for providing high conductivity polysilicon electrodes for self-aligned gate MOSFET devices.
2. Description of the Prior Art
The development of integrated circuit technology has lead to the use of ever decreasing lithographic dimensions and vertical device scaling to provide higher levels of integration. The inherent resulting relative increase in propagation delay has placed great importance on interconnection technology, particularly when multiple levels of interconnection metallurgy are used. Polycrystalline silicon (polysilicon) has been extensively used in MOSFET technologies because of its high temperature stability and its ability to provide a stable self-passivation insulation by direct oxidation. One undesirable characteristic of polysilicon is its relatively high resistivity, on the order of 500 microohm-cm.
Three alternatives to polysilicon interconnect technology have been previously proposed and extensively investigated. Refractory metals such as molybdenum and tungsten, because of their high conductivity, an order of magnitude greater than polysilicon, have been proposed but lack the important ability to provide a stable self-passivating oxide. Alternately, refractory metal silicides have also been proposed, as silicides have relatively high conductivity, high melting points, small grain size and are compatible with silicon dioxide insulating films. Silicides, however, have a limited capability for self-passivation. A third alternative, preserving the electrical interface properties of polysilicon and providing high conductivity of the refractory metal systems was proposed by Rideout, IBM Technical Disclosure Bulletin, November 1974, at pp. 1831-3. In this technique, a layer of silicide forming metal is deposited on previously defined polysilicon gate electrodes to locally form a silicide layer only on the exposed polysilicon. Passivation is achieved by chemical vapor deposition of a layer of silicon dioxide.
An improvement in Rideout's technique is taught in U.S. Pat. No. 4,180,596 to Crowder and Zirinsky in which a refractory metal and silicon are co-evaporated to form a discrete silicide layer, either on silicon dioxide or polysilicon, prior to definition of electrodes. After etching of the desired electrode pattern, the silicide/polysilicide or "polycide" structure is oxidized to provide a silicon dioxide passivation layer. Further experimentation with polycides indicated that the reaction mechanism for the oxidation of polycides was due to the diffusion of silicon from the underlying polysilicon through the silicide layer as opposed to oxidation of the silicides directly, as reported by Zirinsky et al in Applied Physics Letters, Vol. 33, No. 1, July 1, 1978, at pp. 76-78. The application of polycide to MOSFET devices has been described in the IEEE J. Solid-State Circuits, Vol. SC-14, No. 2, April 1979, pp. 291-293.
U.S. Pat. No. 4,128,670 to Gaensslen teaches another method for forming polysilicon-silicide interconnection metallurgy in which sequential layers of polysilicon, a silicide forming metal and polysilicon are deposited over a thin gate dielectric within a single deposition chamber. After definition of electrode patterns the layered structure is exposed to a reoxidation process which simultaneously causes the formation of a layer of silicide intermediate of the two polysilicon layers and also causes the top layer of polysilicon to become partially oxidized. The resulting structure includes gate oxide, polysilicon, silicide, polysilicon and oxidized polysilicon. We have found that such in situ formation of a silicide does not provide optimum high conductivity because of the formation of various silicide phases and the presence of excess free silicon in the structure. The patent does not describe a process in which the thicknesses of the as-deposited layers are specified.
A similar deposition technique in which sequential layers of polysilicon, a refractory metal (titanium) and polysilicon was described by Murarka at the 1979 International Electron Devices Meeting, Washington, D.C., Dec. 3-4-5, 1979, in paper 20.1. Although the purpose of the upper polysilicon is not described in this paper, a subsequent article by Murarka et al, IEEE Transactions on Electron Devices, Vol. ED-27, No. 8, August 1980, pp. 1409-17, indicates that the upper polysilicon was originally intended to provide an etch-resistant protective layer against hydrofluoric acid containing solvents. Experimental results, however, indicated that the desired protection was lost during high temperature processing which caused the upper polysilicon to diffuse through the titanium silicide layer. This not only eliminated the protective layer but also increased the resistivity of the silicide.
Additional, multiple layer polysilicon and silicide-forming metal structures are taught by Howard in IBM Technical Disclosure Bulletin, Vol. 21, No. 7, December 1978, pp. 2811, which describes the use of rare earth silicides to form polycide gate electrodes for MOSFET devices.
In the article, "Oxidation Induced Voids in Polysilicon/Silicide Films," by co-inventors Hsieh and Nesbit, presented at the Spring Meeting of the Electrochemical Society, St. Louis, Mo., May 11-16, 1980, Abstract No. 161, it was reported that the oxidation of polycide structures was found to produce voids in the underlying polysilicon due to the rapid diffusion of silicon through the silicide during oxidation. The presence of such voids seriously impacts the reliability of MOSFET devices using polycide gate structures.
In a related paper by Ishag and co-inventors Koburger and Geipel, Spring Meeting of the Electrochemical Society, St. Louis, Mo., May 11-16, 1980, Abstract No. 162, the gate dielectric breakdown voltage for oxidized polycide gate MOSFET was shown to be dependent upon the thickness of the polysilicon underlying the silicide layer.
Additional references related to polysilicon/silicide-forming metal electrode systems include U.S. Pat. No. 3,381,182 to Thornton which generally teaches the oxidation of a polysilicon layer over a refractory metal or silicide layer for purposes of passivating conductive lines buried in a substrate. U.S. Pat. No. 4,228,212 to Brown et al teaches a method of providing an oxide passivated refractory metal line by depositing polysilicon over a predefined metal line, heating to form a silicide and then oxidizing the polysilicon and a part of the silicide layer to form a passivating layer.
Additional uses of polysilicon in interconnection metallurgy systems are taught in U.S. Pat. No. 3,881,971 to Greer et al which describes a process which includes deposition of silicon on an aluminum layer followed by deposition of a passivating layer of insulating material, in order to presaturate the aluminum with silicon to prevent spiking of aluminum in pn-junctions, and U.S. Pat. No. 4,152,823 to Hall which teaches a metallurgy system including sequentially deposited layers of silicon, refractory metal and silicon in order to provide a silicon interface between the metallurgy and the underlying silicon substrate and between an overlying aluminum line.